The present invention relates generally to level-shifting circuits having a first power supply voltage level and a different second power supply voltage level and also relates to using techniques that essentially prevent current leakage that causes indeterminate voltage/logic levels during circuit operation when one of the supply voltage levels is at a low level and the other supply voltage level is at a high level. More particularly, the invention relates to level shifting circuitry the operation of which is independent of the order of ramping of the two power supply voltages.
In FIG. 1, conventional level-shifting circuit 1-1 includes a CMOS inverter INV1 having its input coupled to receive an input signal VIN and its output connected by a conductor or node ND3 to the input of another CMOS inverter INV2 and also to the gate of a N-channel transistor MN1 having its source connected to ground. The output of inverter INV2 is connected by a conductor ND4 to the gate of a N-channel transistor MN2 having its source connected to ground. CMOS inverters INV1 and INV2 are coupled between a first power supply voltage VSUPPLY1 and ground or VSS. The drain of transistor MN1 is connected by node ND1 to the drain of a P-channel transistor MP1 and the gate of a P-channel transistor MP2. The sources of transistors MP1 and MP2 are connected to a second supply voltage VSUPPLY2. The gate of transistor MP1 is connected by a node or conductor ND2 to the drains of transistors MP2 and MN2 and to the gate electrodes of a CMOS output inverter including a P-channel transistor MP5 and a N-channel transistor MN5. The source of transistor MP5 is connected to VSUPPLY2 and its drain is connected by a VOUT conductor 6 to the drain of transistor MN5, the source of which is connected to ground. During normal operation, transistors MP1, MP2, MN1 and MN2 form a level shifter. Transistors MP1 and MP2 are “latching transistors” that form the latching portion of the level shifter which also includes N-channel selection transistors MN1 and MN2. In the case wherein VSUPPLY1 is at a high or ON voltage level, transistors MN1 and MN2 are driven in response to VSUPPLY1, causing them to control latching transistors MP2 and MP1 by controlling the voltages on nodes ND1 and ND2, respectively. When the gate of one of the latching transistors MP1 or MP2 is pulled to a low voltage level, the drain of that transistor MP1 or MP2 is driven high to the VSUPPLY2 level. This in turn couples VSUPPLY2 to the gate of the opposite latching transistor MP2 or MP2, turning it off. This operation generates “determinate” or predetermined logic levels on nodes ND1 and ND2.
However, in the case wherein VSUPPLY1 is at a low OFF voltage level and the second supply voltage VSUPPLY2 is at a high ON voltage level, it can be seen in Prior Art FIG. 1 that circuit nodes ND1 and ND2 are high impedance nodes which are at indeterminate voltage levels and indeterminate logic states when the first supply voltage. Under these indeterminate voltage levels and logic states, latching transistors MP1 and MP2 no longer operate as part of the above-mentioned standard level shifter that produces determinate logic levels at its outputs. This can lead to CMOS inverter “shoot-through” current dissipation in the CMOS output inverter consisting of P-channel transistor MP5 and N-channel transistor MN5 which generates the output voltage VOUT on conductor 6. Nodes ND3 and ND4 in FIG. 1 also are high impedance nodes, and have voltages between 0 volts and approximately one MOS diode voltage VT above ground (VSS). This causes N-channel transistors MN1 and MN2 to be OFF, but if the voltages of both nodes ND1 and ND2 maintain a weak inversion bias level in either of P-channel transistors MP1 and MP2, this may cause a shoot-through current to flow from the VSUPPLY2 to ground. Under these conditions, VOUT may be at an indeterminate voltage and an indeterminate logic level.
Referring next to the prior art level-shifting circuit 1-2 in FIG. 2, it can be seen that transistors MP1 and MN1 are both ON and provide known or determinate voltage levels and logic levels when VSUPPLY1 is at a low OFF level and VSUPPLY2 is at a high ON level. The prior art two-supply level shifting circuit 1-2 shown in FIG. 2 attempts to address the above-described shoot-through current problem and the indeterminate voltage/logic levels of level-shifting circuit 1-1 in Prior Art FIG. 1 by providing an additional P-channel transistor MP3 having its source coupled to VSUPPLY2 through a current-limiting MOS resistor R0. The drain of transistor MP3 is connected to node ND2, and its gate is connected to node ND4. The gate of MOS resistor R0 is connected to the body electrodes of transistors MP2 and MP3. The circuit shown in FIG. 2 also differs from the circuit shown in FIG. 1 by including a N-channel transistor MN3 having its gate connected to node ND2, its source connected to ground, and its drain connected to node ND1. During normal operation, transistors MP1 and MP2 form the latch portion of a level shifter which generates determinate logic levels on nodes ND1 and ND2.
However, if the value of VSUPPLY2 minus VSUPPLY1 is large enough to produce a gate-to-source turn-on voltage on transistor MP3, a shoot-through current will flow through transistor MP3 and through transistor MP1 to ground. The level of this shoot-through current may be controlled by appropriate sizing of current-limiting or degeneration resistor R0. However, for very low desired shoot-through current levels (of the order of tens of nanoamperes), this forces the resistive degeneration to be so great that level shifting circuit 1-2 may have unacceptable shoot-through current leakage when VSUPPLY1 is at its very low OFF value and the voltage of node ND2 has “floated” up to a sufficiently high level to cause transistor MP1 to be in a weak-inversion ON condition. Transistor MN3 functions as a feedback element which is in place when transistor MP3 drives node ND2 high. Specifically, when VSUPPLY1 is OFF its voltage is coupled by conductor ND4 to the gate of transistor MN3, thus pulling node ND1 low. Prior art level-shifting circuit 1-2 of FIG. 2 assumes that nodes ND4 and ND3 will be equal essentially to zero volts at all times when VSUPPLY1 is at a low OFF level. One weakness of prior art level-shifting circuit 1-2 is that the voltages of node conductors ND3 and ND4 can “float up” as a result of parasitic capacitive coupling when VSUPPLY1 is low, and this can create a shoot-through current leakage condition through transistor MN2.
In FIG. 2, for the case where VSUPPLY1 is equal to zero, the output node ND4 of inverter INV2 is in a “floating” high impedance state within a voltage range from ground to 1 CMOS threshold VT above ground. A voltage high enough to cause both P-channel transistor MP3 and N-channel transistor MN2 to go into their weak inversion conditions can easily be coupled to node ND4. Inverter INV1 is “immune” to shoot-through currents when VSUPPLY1 is essentially equal to zero, but the voltage of node ND3 can float upward and may cause transistor MP1 to be a leakage source. When this occurs, the cross-coupled P-channel transistors MP1 and MP2 can both be in their ON conditions but nevertheless in a non-latched condition. This can result in the gate voltage on node ND1 driving the output inverter transistor pair MN4/MP4 and the gate voltage on node ND2 driving the output inverter transistor pair MN5/MP5 so as to produce indeterminate levels, respectively, between VSUPPLY2 and VSS. This can result in an unacceptably high amount of shoot-through current flowing from VSUPPLY2 to VSS so that the outputs VOUT and VOUTZ are at indeterminate voltage levels and logic states.
The standard prior art cross-coupled P-channel level shifters do not have circuit topologies that avoid the above mentioned shoot-through currents when VSUPPLY1 is OFF and consequently do not have reliable known output logic levels when VSUPPLY1 is OFF.
It should be understood that the need for independence from power-supply ramp-up order is necessary in systems that rely on one of multiple power supplies to, in effect, act as an external master power-on reset signal. The MIPI[rffe] serial communication specification requires the VIO supply voltage (i.e., Vsupply1 in subsequently described FIG. 3) that is provided by a master MIPI communication controller to act as both the serial port supply as well as a master reset signal.
It should be noted that the MIPI Alliance is a global, collaborative organization comprised of companies that span the mobile “ecosystem” and are committed to defining and promoting interface specifications for mobile devices. A broad portfolio of interface specifications from the MIPI Alliance enables design engineers to efficiently interconnect essential components in a mobile device, from the modem and antenna to the peripherals and application processor. Most state-of-the-art smart phones employ at least two MIPI specifications. Some products employ MIPI specifications for a full range of internal connections. MIPI specifications have enabled manufacturers to simplify the design process, reduce design costs, create economies of scale that lower price points, and shorten time-to-market for components, features, and services. Fundamentally, every MIPI specification addresses the industry needs for three characteristics that are essential for any successful mobile design: low power consumption, high-performance operations, and low electromagnetic interference (EMI). MIPI currently has a pair of high-speed physical-layer (PHY) specifications, M-PHY and D-PHY, to support a full range of application requirements in mobile terminals.) In the case that VIO supply voltage is powered down and a separately regulated VCC supply is powered up, the level shifters that normally translate between VIO levels to VCC logic levels must function appropriately to provide a master reset to the rest of the integrated circuit chip. Despite the fact that there is no VIO power, the level-shifter circuit should draw no significant current due to high-impedance “floating” nodes in the circuit and the output of the level shifter should be ensured.
Thus, there is an unmet need for a way of avoiding shoot-through currents in a CMOS level shifting circuit that is powered by multiple power supplies.
There also is an unmet need for a way of avoiding shoot-through currents in a CMOS level shifting circuit that is powered by multiple power supplies wherein the voltage provided by the power supplies is at an inactive or OFF level and the voltage provided by another of the power supplies is at an active or ON level.